RISC, CISC and pipelining
Introduced| English | Meaning |
|---|---|
| CISC/sɪsk/ | Many complex variable-length instructions, more per instruction · RISC: few simple fixed-length instructions, load and store only, many registers, one cycle each. |
| RISC/rɪsk/ | RISC |
| pipelining/ˈpaɪplaɪnɪŋ/ | pipelining |
| Flynn's taxonomy/flɪnz tækˈsɒnəmi/ | A classification of computer architectures according to their numbers of simultaneous instruction streams and data streams. |
| register/ˈredʒɪstə/ | A small, fast storage location within a processor used to hold data, addresses or instructions temporarily. |
| ALU/ˌeɪ el ˈjuː/ | The part of a processor that performs arithmetic and logical operations. |
| hazard/ˈhæzəd/ | A condition preventing a processor pipeline from proceeding as planned, such as a data dependency, branch uncertainty or resource conflict. |
| SIMD/ˈsɪmdiː/ | One instruction operates on many data items at once. This is a GPU or a CPU's vector unit, and it suits images, video and scientific arrays. |
| MIMD/ˈmɪmdiː/ | A computer architecture in which multiple processors can execute different instruction streams on different data. |
| massively parallel/ˈmæsɪvli ˈpærəlel/ | Describing a system that uses a very large number of processing units to work on parts of a computation simultaneously. |
| supercomputers/ˌsuːpəkəmˈpjuːtəz/ | Computers designed for exceptionally large computational workloads, commonly using many processors working in parallel. |
The phone in your pocket does not run Intel
- For thirty years the fastest processors were the most complicated ones: add instructions, and each one does more work. Intel built an empire on it.
- Then a small British company put a deliberately simple processor in a phone. Fewer instructions, all the same length, almost none touching memory. It could not do as much per instruction, and it won anyway.
- It won because simple, uniform instructions can be overlapped, and overlapping is worth more than complexity.
- This lesson is CISC 复杂指令集 and RISC 精简指令集, pipelining 流水线, the four architectures of Flynn's taxonomy, and where a processor's heat and speed limits lead.
CISC and RISC
- A CISC, Complex Instruction Set Computer, has many, often complex instructions: one may perform several memory accesses and operations. They are of variable length, so decoding is intricate. It does more per instruction, in hardware. Example: Intel x86.
- A RISC, Reduced Instruction Set Computer, has a small set of simple instructions, each doing one basic operation, all of fixed length and quick to decode. Only load and store touch memory; everything else is register 寄存器 to register. Example: ARM.
- RISC programs are longer, but each instruction is quick and predictable, which is exactly what a pipeline needs.
More per instruction, or faster and more predictable per instruction
A RISC processor is characterised by:
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RISC keeps instructions few, simple and fixed-length (usually 1 cycle); CISC has many complex variable-length ones.
The differences the exam wants
| Feature | CISC | RISC |
|---|---|---|
| instruction set | many, complex | few, simple |
| instruction length | variable | fixed |
| memory access | many instructions may access memory | only load and store |
| registers | fewer | many |
| cycles per instruction | varies | usually one |
| pipelining | harder | natural |
- Modern Intel chips translate their CISC instructions into simpler RISC-like micro-operations internally, which is the clearest evidence of which design won the argument.
Match each term to its description.
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RISC = simple + fixed-length + load/store; CISC = complex + variable-length; pipelining overlaps stages for speed.
In a RISC processor, the only instructions that access memory are load and ____.
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Everything else is register to register. That restriction is what makes instructions fixed-length, uniform in timing and easy to pipeline.
Pipelining
- A pipeline processes instructions in overlapping stages, like an assembly line: fetch, decode, execute in the ALU 算术逻辑单元, memory access, write back.
- Each stage works on a different instruction at the same time, so once the pipeline is full, one instruction completes per cycle.
- It does not make any single instruction faster. It increases throughput: more instructions finish per second.
- RISC's fixed-length, simple instructions make every stage take the same time, which is why RISC pipelines cleanly and CISC does not.
Six instructions in flight, one finishing each cycle
How pipelining fills up
Step through the clock cycles. Once the pipeline is full, a new instruction finishes every cycle — even though each one still takes several stages — because the stages of different instructions overlap.
When a pipeline is full, it completes about:
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Overlapping the stages means a new instruction finishes each cycle once the pipeline is full.
Pipelining speeds up a processor by:
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Stages of different instructions run at the same time.
Worked example: why pipelining is faster
- A five-stage pipeline runs at one cycle per stage. Explain why it is faster than executing instructions one after another.
- Without a pipeline, each instruction occupies the processor for all five stages, so one finishes every five cycles.
- With a pipeline, the fetch unit starts the next instruction while the current one is still decoding, so five instructions are in progress at once and, once it is full, one completes every cycle.
- No individual instruction is executed faster; the throughput rises about fivefold. Say that explicitly: it is the mark most often missed.
What does pipelining actually improve?
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Stages overlap, so five instructions are in progress at once and one completes per cycle. No individual instruction is executed any faster.
Hazards
- A hazard 冒险 stalls the pipeline. A data hazard occurs when an instruction needs a result the previous one has not yet produced, so it must wait.
- A control hazard occurs at a branch: until the branch is resolved, the processor does not know which instruction to fetch next.
- Both waste cycles, which is why processors predict branches and forward results between stages.
A data hazard stalls the pipeline when an instruction needs a result that is not ready yet; a control hazard comes from a branch changing which instruction runs next.
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Hazards force the pipeline to stall (or flush), which is why they reduce the ideal one-per-cycle throughput.
Match each pipeline hazard to what causes it.
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Both stall the pipeline and waste cycles, which is why processors forward results between stages and predict branches.
Flynn's taxonomy
- Flynn's taxonomy 弗林分类 sorts computers by how many instruction streams and data streams they have.
- SISD: one instruction stream, one data stream, a traditional single core.
- SIMD 单指令多数据: one instruction operates on many data items at once. This is a GPU or a CPU's vector unit, and it suits images, video and scientific arrays.
- MISD: several operations on the same data; rare and mostly theoretical. MIMD 多指令多数据: many processors run different instructions on different data, which is a multi-core CPU or a cluster, and it is the most general.
One instruction, many data items
Which describe SIMD? Select all that apply.
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Different programs on different data is MIMD, the multi-core case. SIMD is one instruction stream over many data streams.
Massively parallel computers
- A massively parallel 大规模并行 system uses thousands of processors connected by a fast network, each with its own memory, exchanging data by messages rather than sharing memory.
- It is MIMD, and it needs specially written software, because the programmer must divide the problem and manage the communication.
- This is what the largest supercomputers 超级计算机 are: climate simulation, machine-learning training and astrophysics all run this way.
A massively parallel computer's processors share one block of memory.
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Each processor has its own memory, and they exchange data by messages over a fast network. That distributed memory is what the term means.
Worked example: place the machine
- A graphics card applies the same brightness adjustment to two million pixels. SIMD: one instruction, many data items, which is precisely what the GPU's thousands of small cores are built for.
- A four-core laptop runs a browser, a compiler and a music player at once. MIMD: different instructions on different data, one stream per core.
- A weather centre divides the atmosphere into a grid across ten thousand processors, each with its own memory, passing boundary values as messages. Massively parallel, which is a form of MIMD.
- Name the category, then justify with the number of instruction and data streams.
Marks that slip away
- Pipelining raises throughput; it does not shorten any single instruction. Say so.
- In RISC, only load and store touch memory. That one fact explains the fixed length, the many registers and the clean pipeline.
- SIMD is one instruction on many data; MIMD is many instructions on many data. Count the streams before answering.
- Massively parallel means thousands of processors with distributed memory and message passing, not just "a fast computer".
You've got it
- CISC: many complex variable-length instructions, more per instruction · RISC: few simple fixed-length instructions, load and store only, many registers, one cycle each
- a pipeline overlaps fetch, decode, execute, memory and write-back, so one instruction completes per cycle once full: higher throughput, not faster instructions; data and control hazards stall it
- Flynn: SISD, SIMD (a GPU), MISD, MIMD (multi-core)
- massively parallel: thousands of processors, distributed memory, message passing, MIMD, used by supercomputers