RISC, CISC and pipelining
| English | Chinese | Pinyin |
|---|---|---|
| CISC | 复杂指令集 | fù zá zhǐ lìng jí |
| RISC | 精简指令集 | jīng jiǎn zhǐ lìng jí |
| pipelining | 流水线 | liú shuǐ xiàn |
| hazard | 冒险 | mào xiǎn |
Two CPU philosophies
- Processors come in two design styles: CISC 复杂指令集 and RISC 精简指令集.
- They trade off doing more per instruction against doing each instruction faster.
- Pipelining 流水线 then overlaps instructions for more speed.
Pipelining speeds up a processor by:
Stages of different instructions run at the same time.
CISC vs RISC
| Feature | CISC | RISC |
|---|---|---|
| Instruction set | many, complex | few, simple |
| Instruction length | variable | fixed |
| Memory access | many instructions | only load/store |
| Pipeline-friendly | harder | naturally |
| Cycles per instruction | varies | usually 1 |
- CISC (e.g. x86) does more per instruction in hardware; RISC (e.g. ARM) keeps instructions simple, fixed-length and register-to-register — longer programs but quick, predictable steps.
Pipelining overlaps the stages of six instructions, so one finishes each cycle
A RISC processor is characterised by:
RISC keeps instructions few, simple and fixed-length (usually 1 cycle); CISC has many complex variable-length ones.
Match each term to its description.
RISC = simple + fixed-length + load/store; CISC = complex + variable-length; pipelining overlaps stages for speed.
Pipelining
- A pipeline processes instructions in overlapping stages (Fetch → Decode → Execute → Memory → Write back), like an assembly line.
- Each stage works on a different instruction, so once full, one instruction completes per cycle.
- RISC's fixed-length instructions make every stage take the same time.
- A hazard 冒险 can stall it: a data hazard (a result isn't ready yet) or a control hazard (a branch makes the next address unknown).
A graphics card: its GPU runs the same instruction on many data items at once (SIMD)
How pipelining fills up
Step through the clock cycles. Once the pipeline is full, a new instruction finishes every cycle — even though each one still takes several stages — because the stages of different instructions overlap.
When a pipeline is full, it completes about:
Overlapping the stages means a new instruction finishes each cycle once the pipeline is full.
A data hazard stalls the pipeline when an instruction needs a result that is not ready yet; a control hazard comes from a branch changing which instruction runs next.
Hazards force the pipeline to stall (or flush), which is why they reduce the ideal one-per-cycle throughput.
Why pipelining is faster
Worked example. Like a factory line, pipelining starts fetching the next instruction while the current one is still decoding. The instructions overlap, so more finish per second — without making any single one faster.
- Complex Instruction Set Computers (CISC) have many rich instructions; Reduced Instruction Set Computers (RISC) use few simple fixed-length ones, ideal for pipelining.
CISC has many complex instructions; RISC has few simple ones
You've got it
- CISC = many complex variable-length instructions; RISC = few simple fixed-length, load/store only
- RISC suits pipelining (predictable stages) and uses many fast registers
- a pipeline overlaps stages → ~one instruction completes per cycle
- pipelines stall on data and control hazards