| English | 意味 |
|---|---|
| processor/ˈprəʊsesə/ | プロセッサー |
| registers/ˈredʒɪstəz/ | レジスタ |
| buses/ˈbʌsɪz/ | バス |
| Von Neumann architecture/vɒn ˈnɔɪmən ˈɑːkɪtektʃə/ | フォン・ノイマン型アーキテクチャ |
| Immediate Access Store/ɪˈmiːdɪət ˈækses stɔː/ | 即時アクセスメモリ |
| stored program/stɔːd ˈprəʊɡræm/ | プログラム記憶方式 |
| ALU/ˌeɪ el ˈjuː/ | ALU(演算論理回路) |
| control unit/kənˈtrəʊl ˈjuːnɪt/ | 制御ユニット |
| system clock/ˈsɪstəm klɒk/ | システムクロック |
| clock speed/klɒk spiːd/ | クロック速度 |
| general-purpose registers/ˈdʒenərəl ˈpɜːpəs ˈredʒɪstəz/ | 汎用レジスタ |
| special purpose registers/ˈspeʃl ˈpɜːpəs ˈredʒɪstəz/ | 専用レジスタ |
| Program Counter/ˈprəʊɡræm ˈkaʊntə/ | プログラムカウンタ |
| Memory Address Register/ˈmeməri əˈdres ˈredʒɪstə/ | メモリアドレスレジスタ |
| Memory Data Register/ˈmeməri ˈdeɪtə ˈredʒɪstə/ | メモリデータレジスタ |
| Current Instruction Register/ˈkʌrənt ɪnˈstrʌkʃn ˈredʒɪstə/ | 現在指令レジスタ |
| accumulator/əˈkjuːmjʊleɪtə/ | 累加器 |
| Index Register/ˈɪndeks ˈredʒɪstə/ | インデックスレジスタ |
| Status Register/ˈsteɪtəs ˈredʒɪstə/ | ステータスレジスタ |
| flag/flæɡ/ | フラグ |
| address bus/əˈdres bʌs/ | アドレスバス |
| data bus/ˈdeɪtə bʌs/ | データバス |
| control bus/kənˈtrəʊl bʌs/ | 制御バス |
| register transfer/ˈredʒɪstə ˈtrænsfɜː/ | レジスタ転送 |
The report every computer still follows
- In June 1945 John von Neumann circulated a typed draft describing a machine that had not yet been built: the EDVAC.
- Its idea was simple and new. Keep the program in the same memory as the data, and have one processor fetch and carry out the instructions one at a time.
- The draft was never finished, but the design was copied everywhere. Your phone, your laptop and the school server are all built on it.
- This lesson takes the model apart: the memory, the processor's parts, its registers and the buses between them.
The Von Neumann model
- The Von Neumann architecture 冯·诺依曼体系结构 has a single memory, the Immediate Access Store 立即存取存储器 (IAS), holding both program instructions and data. That is the stored program 存储程序 concept.
- The processor 处理器 fetches each instruction from memory and executes it, one at a time, in address order unless a branch instruction changes the flow.
- Instructions, data and addresses all travel between processor and memory along shared buses 总线.

One memory, one processor, three buses
Why the stored program matters
- Change the program in memory and the same hardware does a different job. No rewiring, no new machine.
- A program is just data until it is fetched, so it can be loaded from a disk, sent over a network or written by another program.
- The exam wording: instructions and data are stored in the same memory, and instructions are fetched one at a time and executed by the processor.
格納プログラム方式(Von Neumann)の発想とは、以下の通りです:
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単一のメモリが命令とデータを一緒に保持しており、格納されたプログラムを変更することで、配線の変更なしにコンピュータの動作を変えられます。
ALU, control unit and clock
- The ALU 算术逻辑单元 (Arithmetic and Logic Unit) does the arithmetic (add, subtract) and the logic (AND, OR, comparisons), taking operands from registers and putting the result back in one.
- The control unit 控制单元 (CU) decodes each instruction and sends the control signals that carry it out: opening data paths, telling the ALU what to do, ordering memory reads and writes.
- The system clock 系统时钟 sends a steady stream of pulses. The control unit moves the cycle on one step per pulse, so every part changes state together; the clock speed 时钟频率, in GHz, is the number of pulses a second.

The whole processor is one small chip
ALU が担当するのは:
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算術論理回路は計算および論理・比較を行います。命令のデコードは制御ユニットの仕事です。
____ ユニットが各命令をデコードし、それを実現するための制御信号を送信します。
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制御ユニットはデコードと信号送出を行い、ALU は算術・論理演算を行い、クロックがこれらを同期させています。
The registers
- Registers 寄存器 are tiny, very fast stores inside the processor. General-purpose registers 通用寄存器 hold the programmer's temporary values. Special purpose registers 专用寄存器 each have one fixed job in the cycle.
| Register | Job |
|---|---|
| Program Counter 程序计数器 (PC) | the address of the next instruction to be fetched |
| Memory Address Register 内存地址寄存器 (MAR) | the address of the location being read from or written to |
| Memory Data Register 内存数据寄存器 (MDR) | the data or instruction just read from, or about to be written to, that location |
| Current Instruction Register 当前指令寄存器 (CIR) | the instruction currently being decoded and executed |
| Accumulator 累加器 (ACC) | the result of the last arithmetic or logic operation |
| Index Register 变址寄存器 (IX) | an offset added to an address in indexed addressing |
| Status Register 状态寄存器 | the flags set by the last operation |

Registers, control unit and ALU, linked by the buses
Von Neumann コンピュータの各部分にタップしてください
各ブロックを調べましょう。CPU(制御ユニット、ALU、レジスタ)はバスを介して単一のメインメモリと通信し、命令とデータの両方を共有するこの単一メモリーが Von Neumann の発想です。
各専用レジスタが保持する内容にマッチさせなさい。
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PC は次の指令を指し示し、CIR は現在の指令を保持し、MAR/MDR はメモリのアドレス/データペアであり、ACC は現在の計算結果を保持しています。
Worked example: "describe the role of each register"
- The table question wants one precise sentence per register, and the words that earn the marks are in bold.
- PC: holds the address of the next instruction to be fetched. MAR: holds the address of the location being accessed.
- MDR: holds the data just read from, or about to be written to, memory. CIR: holds the instruction currently being decoded and executed.
- ACC: holds the result of the last ALU operation. Notice that two registers hold addresses, two hold contents, and one holds a result.
The status register's flags
- Each flag 标志 is one bit, set or cleared by the ALU after an operation: the zero flag when a result or comparison gives zero, the carry flag when an addition overflowed the register, the negative flag when a result is negative, the overflow flag when a signed result does not fit.
- A conditional jump reads a flag to decide whether to branch. That is how
IFand loops reach the hardware. - An overflow flag can also raise an interrupt, which the next lesson handles.
ステータスレジスタに含まれるフラグはどれですか?すべて選択してください。
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キャリー、ゼロ、ネガティブ、オーバーフローは ALU によって設定される 1 ビットフラグです。プログラムカウンタはアドレスを保持する別のレジスタです。
The three buses
- The address bus 地址总线 carries the address the processor wants. It is one-way, processor to memory.
- The data bus 数据总线 carries the data or instruction itself. It is two-way, because reads and writes go in opposite directions.
- The control bus 控制总线 carries control signals such as read, write, clock and interrupt. It is two-way.

The three system buses connecting processor, memory and input/output
片方向(一方通行)のバスはどれですか?
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アドレスバスは片方向です(CPU → メモリ)。データバスと制御バスは双方向です。
Worked example: how wide is wide enough?
- An $n$-bit address bus can address $2^{n}$ locations. A 16-bit bus reaches $2^{16} = 65\,536$ locations; a 32-bit bus reaches $2^{32}$, about four billion.
- "State one effect of increasing the width of the address bus": more memory locations can be addressed.
- "State one effect of increasing the width of the data bus": more bits move in each transfer, so fewer transfers are needed for the same data.
- Widen the address bus and you can have more memory; widen the data bus and you move it faster.
16ビットのアドレスバスがアクセスできるメモリ領域はいくつありますか?
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$2^{16} = 65\,536$ 個の領域。
広いアドレスバスは、CPU がより多くのメモリ領域をアドレス指定できるようにします。
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追加されるアドレスラインごとに到達範囲が倍増します — n本のラインで 2ⁿ の場所をアドレス指定できます。
Register transfer notation
- Movements between registers and memory are written in register transfer 寄存器传送 notation:
MAR ← [PC]means "copy the contents of the PC into the MAR". - Square brackets mean "the contents of", and
[[MAR]]means "the contents of the location whose address is in the MAR". - The whole fetch-execute cycle is written this way in the next lesson; the notation is the same as the pseudocode assignment arrow.
MAR ← [PC]の意味は何か?
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矢印は目的地を指し、角括弧は「中身」を意味します。これはすべてのフェチプロセスの最初のステップです。
Marks that slip away
- The PC holds the address of the next instruction, not the current one; the CIR holds the instruction, not an address.
- The MAR holds an address, the MDR holds data. Mixing them costs both marks.
- Only the address bus is one-way. Saying "all buses are one-way" or "the data bus is one-way" is a common slip.
- Registers are inside the processor, not part of RAM, and they are faster than any memory.
プログラムカウンタは現在実行中の指令を保持しています。
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PC は次の指令のアドレスを保持します。現在の指令は CIR にあります。
You've got it
- Von Neumann: one memory (IAS) holds instructions and data; the processor fetches and executes them one at a time
- ALU computes, CU decodes and signals, the clock keeps the steps in time
- PC next address · MAR address being accessed · MDR data · CIR current instruction · ACC result · IX offset · status register flags
- address bus one-way, $2^{n}$ locations; data and control buses two-way;
MAR ← [PC]copies the contents of PC into MAR