Processor Fundamentals

The Von Neumann architecture 冯·诺依曼体系结构 underlies almost every general-purpose computer:

• a single memory — the Immediate Access Store 立即存取存储器 (IAS) — holds both program instructions and data (the stored program 存储程序 concept).
• a processor 处理器 (CPU) fetches instructions from memory and runs them one at a time.
• instructions run in order unless a branch changes the flow.

The stored-program idea is what makes a computer flexible: change the program and you change what it does, with no rewiring.

All of these parts sit inside one small chip. The diagram later in this section shows how they connect; the photo below shows the real thing.

A modern CPU: the whole processor is one small chip (here seen from below, showing the contacts)

The matching CPU socket on the motherboard: the chip's contacts press onto these pins

Arithmetic and Logic Unit (ALU)

The ALU 算术逻辑单元 does the arithmetic (add, subtract, …) and logic (AND, OR, comparisons). It takes operands from registers 寄存器 and puts results back in a register.

Control Unit (CU)

The control unit 控制单元 decodes each instruction and sends the control signals to carry it out — opening data paths, telling the ALU what to do, and controlling memory reads and writes.

System clock

The clock sends a steady stream of pulses that keep the CPU in step. Each instruction takes a fixed number of cycles, and the clock speed 时钟频率 (e.g. 3.8 GHz) is one factor in performance.

Registers

Registers are tiny, very fast stores inside the CPU. The special purpose registers 专用寄存器 each have a fixed job in the cycle:

• Program Counter 程序计数器 (PC) — the address of the next instruction.
• Memory Address Register 内存地址寄存器 (MAR) — the address being read or written.
• Memory Data Register 内存数据寄存器 (MDR) — the data going to or from memory.
• Current Instruction Register 当前指令寄存器 (CIR) — the instruction being decoded.
• Accumulator 累加器 (ACC) — the value the ALU is working on.
• Status Register 状态寄存器 — holds flags 标志 (carry, zero, negative, overflow) used by branches.
• Index Register 变址寄存器 — an offset used in indexed addressing.

General-purpose registers 通用寄存器 are used by the programmer for temporary values during a calculation. Movements of data between registers and memory are written in register transfer 寄存器传送 notation — e.g. MAR ← [PC] ("copy the contents of PC into MAR").

The Von Neumann CPU: registers, control unit and ALU linked by buses

Three internal buses 总线 (sets of parallel wires) connect the parts:

• address bus 地址总线 — carries the memory address. One-way (CPU → memory).
• data bus 数据总线 — carries the data. Two-way.
• control bus 控制总线 — carries control signals (read, write, interrupt). Two-way.

An $n$-bit address bus can reach $2^{n}$ memory locations. The data-bus width sets how many bits move per access (often the word size).

The three system buses connecting the CPU, memory and input/output

• clock speed — more cycles per second.
• number of cores 核心 — a multi-core CPU runs several threads at once.
• word size 字长 — a 64-bit CPU handles 64-bit chunks per cycle and can address far more memory than a 32-bit one.
• amount of RAM 随机存取存储器 — more RAM holds more of the working set; too little forces the OS to page 分页 to disk.
• cache memory 高速缓存 size — more cache cuts average memory access time.
• secondary storage 辅助存储器 type — an SSD loads programs far faster than an HDD.
• bus width and speed — wider/faster buses move data more quickly.

Match the specs to the workload: a quad-core beats a dual-core on parallel work, but higher per-core speed wins on single-threaded work.

A port 端口 is a physical socket for connecting a peripheral 外围设备:

• USB (Universal Serial Bus) — general-purpose (keyboards, drives, phones).
• HDMI (High Definition Multimedia Interface) — digital video and audio to a screen.
• VGA (Video Graphics Array) — older analogue video output to a monitor.
• Ethernet (RJ-45) — wired LAN. Audio jacks — headphones/microphone.

Different ports use different signals, so an HDMI cable will not fit a USB socket. USB-C is unusual in carrying video, data and power.

The CPU repeats the fetch-execute cycle 取指-执行周期, one run per machine instruction.

Fetch

1. the PC's address is copied to the MAR.
2. the PC is incremented to point to the next instruction.
3. a read signal goes over the control bus.
4. memory puts the instruction on the data bus.
5. it is copied into the MDR, then into the CIR.

The register transfers in a fetch: PC → MAR → memory → MDR → CIR, with the PC incremented

Decode

The CU decodes the instruction in the CIR — what operation, and which operands or addresses.

Execute

The CU carries it out: arithmetic/logic goes to the ALU (result to the ACC); a load/store moves data between memory and a register; a branch changes the PC. Then the cycle repeats.

The fetch-execute cycle, with a check for interrupts each time

An interrupt 中断 is a signal that pauses the normal cycle so the CPU can handle an urgent event (a key press, a packet arriving, a hardware fault, division by zero, the OS timer).

Handling one:

1. finish the current instruction.
2. save the state (PC and registers).
3. load the address of the interrupt service routine 中断服务程序 (ISR) into the PC and run it.
4. the ISR handles the event.
5. restore the saved state and carry on.

Interrupts let the system respond promptly without the CPU constantly checking devices, and are how the OS multitasks.

How an interrupt fits into the fetch-execute cycle

The CPU actually runs machine code 机器码 — bit patterns, specific to one architecture. Assembly language 汇编语言 is a readable form, with one instruction per machine instruction, written using mnemonics 助记符 like LDD, ADD, JMP. An assembler 汇编器 translates it to machine code.

An assembler turns mnemonics into machine-code bit patterns

Two-pass assembler

A two-pass assembler reads the source twice:

• pass 1 builds a symbol table 符号表: each time a label 标签 (like LOOP:) appears, record its address; no code yet.
• pass 2 generates code: translate each instruction, and when one refers to a label (like JMP LOOP), look up its address in the symbol table.

Two passes handle forward references 前向引用 (a jump to a label defined later).

Example instruction set

Cambridge uses a small generic set: data movement (LDD, LDM, LDI, LDX, STO, MOV), arithmetic (ADD, SUB, INC, DEC), logic/bit (AND, OR, XOR, LSL, LSR), compare and branch (CMP, JMP, JPE, JPN), I/O (IN, OUT), and END. The exact mnemonics are given in the paper's reference table.

The addressing mode 寻址方式 (the modes of addressing) says how the CPU finds the operand:

• immediate addressing 立即寻址 — the operand is the value in the instruction. LDM #10 loads 10.
• direct addressing 直接寻址 — the instruction holds an address; the operand is the value there. LDD 200.
• indirect addressing 间接寻址 — the instruction holds an address that holds another address, which is the data. LDI 200.
• indexed addressing 变址寻址 — effective address is address + index register; used for arrays. LDX 100 with IR = 5 reads address 105.

(Relative addressing 相对寻址 gives the address as an offset from the PC — used for jumps.)

How each addressing mode reaches its operand — immediate, direct, indirect and indexed

Worked example. Memory holds: location 200 = 250, location 250 = 99, location 105 = 7. The index register holds 5. What is in the accumulator after each of LDM #200, LDD 200, LDI 200 and LDX 100? Follow how far each mode has to look. LDM #200 is immediate - the operand is the number written in the instruction, so the accumulator holds 200. LDD 200 is direct - go to location 200 and take what is there: 250. LDI 200 is indirect - location 200 holds 250, which is another address, so go on to location 250: 99. LDX 100 is indexed - add the index register to the address, $100 + 5 = 105$, and read location 105: 7. Count the hops to keep them apart: immediate 0, direct 1, indirect 2, indexed 1 (once the index has been added).

To trace it: make a table with columns for the PC, ACC, index register, each variable and any flags. Step through the instructions, updating the table after each; follow branches when they change the PC; stop at END. A common pattern is a loop over an array using indexed addressing.

A logical shift 逻辑移位 moves all the bits left or right by some places, filling new positions with 0.

• left shift by 1 (LSL #1) — bits move left, a 0 enters on the right; for an unsigned number this is × 2.
• right shift by 1 (LSR #1) — bits move right, a 0 enters on the left; for an unsigned number this is integer ÷ 2.

Shifting by $n$ places multiplies or divides by $2^{n}$. Example: 00001011 (11) LSL #1 → 00010110 (22).

An arithmetic right shift keeps the sign bit so a negative signed number stays negative. A cyclic shift 循环移位 (rotate) feeds the bit that drops off one end back in at the other end, so no bits are lost.

Logical left ($\times 2$), logical right ($\div 2$) and arithmetic right (keeps the sign bit)

Bit manipulation for monitoring/control

Embedded devices often use one bit 位 of a register per signal (e.g. bit $n$ = LED $n$). Using a mask 掩码 — bit masking — you can:

• set bit $n$: R = R OR a mask with bit $n$ set.
• clear bit $n$: R = R AND a mask with bit $n$ clear and the rest set.
• toggle bit $n$: R = R XOR a mask with bit $n$ set.
• test bit $n$: R AND the mask, then check if the result is non-zero.

Set a bit with OR, clear it with AND, toggle it with XOR — each using a mask

Bit manipulation is fast, uses little memory, and lets one byte hold up to 8 on/off states.

• Learn the fetch-execute cycle in register-transfer terms (PC, MAR, MDR, CIR, ACC) and what increments the PC.
• Name each register's job; the address bus is one-way, the data bus is two-way.
• Distinguish the addressing modes (immediate, direct, indirect, indexed) — a frequent question.
• Explain how clock speed, number of cores, cache size and word length affect performance.
• For a binary shift, state whether it is logical or arithmetic; a left shift multiplies by 2, a right shift divides by 2.