Adders and flip-flops · 加法器与触发器
| English | 中文 | Pinyin · 拼音 |
|---|---|---|
| carry/ˈkæri/ | 进位 | jìn wèi |
| half adder/hɑːf ˈædə/ | 半加器 | bàn jiā qì |
| full adder/fʊl ˈædə/ | 全加器 | quán jiā qì |
| flip-flop/flɪp flɒp/ | 触发器 | chù fā qì |
| ripple-carry adder/ˈrɪpl ˈkæri ˈædə/ | 行波进位加法器 | xíng bō jìn wèi jiā fǎ qì |
| bistable/baɪˈsteɪbl/ | 双稳态 | shuāng wěn tài |
| counters/ˈkaʊntəz/ | 计数器 | jì shù qì |
| SRAM/ˈesræm/ | 静态RAM | jìng tài RAM |
| SR flip-flop/ˌes ˈɑː flɪp flɒp/ | SR触发器 | SR chù fā qì |
| JK flip-flop/ˌdʒeɪ ˈkeɪ flɪp flɒp/ | JK触发器 | JK chù fā qì |
| toggle/ˈtɒɡl/ | 翻转 | fān zhuǎn |
How a machine that only knows true and false does arithmetic
- A processor has no adder in the sense of a thing that knows numbers. It has gates that answer true or false, and nothing else.
- Yet $1 + 1 = 10$ falls out of two gates: an XOR gives the sum digit, an AND gives the carry. That is the entire arithmetic unit in miniature, and chaining copies of it adds numbers of any width.
- The other half of a computer is remembering, and one bit of memory is also just gates, wired so that their outputs feed back into their inputs and hold.
- This lesson is the half adder 半加器, the full adder 全加器, and the flip-flop 触发器 that stores a bit.
只懂真与假的机器怎样做算术
- 处理器里没有"懂数字的加法器"这种东西。它只有回答真或假的门,别无其他。
- 然而 $1 + 1 = 10$ 从两个门里就掉了出来:XOR 给出和的那一位,AND 给出进位。这就是整个算术单元的缩影,把它的副本串起来就能加任意宽度的数。
- 计算机的另一半是记忆,而一位内存也不过是门——只是接线时让输出反馈回输入,从而保持住。
- 这一课讲半加器(half adder)、全加器(full adder),以及存一位的触发器(flip-flop)。
The half adder
- A half adder adds two single bits, $A$ and $B$, producing a sum $S$ and a carry 进位 $C$.
| A | B | S | C |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
- Read the columns: $S$ is 1 when exactly one input is 1, which is XOR. $C$ is 1 only when both are 1, which is AND. So $S = A \oplus B$ and $C = A \cdot B$.
- It ignores any carry in, which is why it is only "half" an adder and cannot be chained on its own.
Two gates, and binary addition exists
半加器
- 半加器把两个单独的位 $A$ 和 $B$ 相加,产生一个和 $S$ 和一个进位(carry)$C$。
| A | B | S | C |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
- 读这几列:恰好一个输入为 1 时 $S$ 为 1,这就是 XOR。只有两个都为 1 时 $C$ 才为 1,这就是 AND。所以 $S = A \oplus B$,$C = A \cdot B$。
- 它忽略任何进位输入,这就是它只是"半个"加法器、无法单独串联的原因。

两个门,二进制加法就存在了
The gates inside an adder · 加法器内部的门
A half-adder's sum bit is an XOR gate and its carry is an AND gate — toggle A and B and watch the truth-table row light up. · 半加器的和位是一个 XOR 门,进位是一个 AND 门——切换 A 和 B,看真值表的行点亮。
In a half adder, the sum output S is produced by which gate? · 在一个半加器中,和输出 S 由哪个门产生?
$S = A \text{ XOR } B$ (1 when the inputs differ); the carry is $A \text{ AND } B$. · $S = A \text{ XOR } B$(输入不同时为 1);进位是 $A \text{ AND } B$。
In a half adder the carry output C is produced by which single gate? · 在半加器中,进位输出 C 由哪一个门产生?
C is 1 only when both inputs are 1, which is AND. The sum S is 1 when exactly one input is 1, which is XOR. · 只有两个输入都为 1 时 C 才为 1,这就是 AND。恰好一个输入为 1 时和 S 为 1,那是 XOR。
The full adder
- A full adder adds three bits: $A$, $B$ and a carry-in, producing a sum and a carry-out. $S = A \oplus B \oplus C_{\text{in}}$.
- It can be built from two half adders plus an OR gate: the first half adder adds $A$ and $B$, the second adds that sum to the carry-in, and the OR combines the two carries.
- Chain full adders so that each carry-out feeds the next carry-in, and you have a multi-bit ripple-carry adder 行波进位加法器: four of them add two 4-bit numbers.
The carry is what has to travel, which is why it is called ripple
全加器
- 全加器把三个位相加:$A$、$B$ 和一个进位输入,产生一个和与一个进位输出。$S = A \oplus B \oplus C_{\text{in}}$。
- 它可以由两个半加器加一个 OR 门构成:第一个半加器把 $A$ 和 $B$ 相加,第二个把那个和与进位输入相加,OR 门把两个进位合并。
- 把全加器串起来,每个的进位输出接下一个的进位输入,就得到多位的行波进位加法器(ripple-carry adder):四个就能把两个 4 位数相加。

要传播的是进位,这就是"行波"这个名字的由来
Match each building block to what it does. · 把每个构建块与它做的事配对。
Adders add bits (chain full adders for multi-bit addition); flip-flops store a bit (the JK fixes the SR forbidden state). · 加法器加位(链接全加器做多位加法);触发器存储一个位(JK 修复 SR 的禁止状态)。
How does a full adder differ from a half adder? · 一个全加器与一个半加器有什么不同?
A full adder adds A, B and a carry-in (so adders can be chained) — built from two half adders plus an OR gate. · 一个全加器加 A、B 和一个进位输入(所以加法器能被链接)——从两个半加器加一个 OR 门构建。
Worked example: why a full adder, not two half adders
- Explain why a 4-bit adder is built from full adders rather than half adders.
- Adding two 4-bit numbers column by column, every column except the rightmost may receive a carry from the column to its right, so it has three inputs to add, not two.
- A half adder has no carry-in, so it cannot take that third input, and the carry would simply be lost.
- Only the least significant column has no carry-in, so a half adder would do there; in practice all four are full adders, with the first carry-in tied to 0.
例题:为什么用全加器而不是半加器
- 解释 4 位加法器为什么用全加器而不是半加器构成。
- 把两个 4 位数逐列相加时,除了最右一列,每一列都可能收到来自右边一列的进位,所以它要相加的是三个输入,不是两个。
- 半加器没有进位输入,接不下第三个输入,进位就会直接丢失。
- 只有最低位那一列没有进位输入,那里用半加器是可以的;实际中四个都用全加器,把第一个进位输入接到 0。
Why must a 4-bit adder use full adders rather than half adders? · 4 位加法器为什么必须用全加器而不是半加器?
A half adder does produce a carry; what it lacks is a carry-in, so it cannot accept the carry arriving from the previous column. · 半加器是能产生进位的;它缺的是进位输入,所以接不下从前一列传来的进位。
Put the construction of a 4-bit ripple-carry adder in order. · 把 4 位行波进位加法器的构造过程按顺序排列。
Gates make a half adder, half adders make a full adder, full adders chain into a word-width adder. The carry rippling along is what gives it its name. · 门构成半加器,半加器构成全加器,全加器串成字宽的加法器。进位沿着它传播,这就是它名字的由来。
Flip-flops
- A flip-flop is a bistable 双稳态 circuit: it has two stable states, 0 and 1, and it remembers the one it is in. It stores exactly one bit.
- It is the basic element of registers, where $n$ bits means $n$ flip-flops, of counters, and of SRAM 静态RAM cells.
- Unlike an adder, whose output depends only on its inputs now, a flip-flop's output depends on its past inputs. That is what memory means at the circuit level.
触发器
- 触发器是双稳态(bistable)电路:它有两个稳定状态 0 和 1,并记住自己所处的那个。它恰好存一位。
- 它是寄存器的基本元件——$n$ 位就是 $n$ 个触发器——也是计数器和 SRAM(静态RAM)单元的基本元件。
- 与加法器不同——加法器的输出只取决于此刻的输入——触发器的输出取决于它过去的输入。这就是电路层面上"记忆"的含义。
A flip-flop is used to: · 一个触发器用来:
A flip-flop has two stable states and holds one bit — the building block of registers and SRAM. · 一个触发器有两个稳定状态并保存一个位——寄存器和 SRAM 的构建块。
A flip-flop is bistable — it has two stable states and remembers one bit — which makes it the building block of registers and SRAM. · 一个触发器是双稳态的——它有两个稳定状态并记住一个位——这使它成为寄存器和 SRAM 的构建块。
Chaining flip-flops gives registers and counters; SRAM cache is built from them (no refresh needed, unlike DRAM). · 链接触发器给出寄存器和计数器;SRAM 缓存由它们构建(不需要刷新,不像 DRAM)。
SR and JK
- An SR flip-flop SR触发器 has inputs S (set) and R (reset) and outputs $Q$ and $\overline{Q}$, built from two cross-coupled NOR gates.
S=1, R=0sets $Q$ to 1.S=0, R=1resets $Q$ to 0.S=0, R=0holds the current state, which is the memory.S=1, R=1is invalid: it asks for set and reset at once.- A JK flip-flop JK触发器 removes that flaw by giving the
1,1input a meaning: toggle 翻转, so the output flips to its opposite. That makes it ideal for counters 计数器, since a chain of toggling flip-flops counts in binary. - A JK is usually clocked: the inputs act only on a clock edge, which keeps every flip-flop in the machine in step.
The invalid input turned into a useful one
SR 与 JK
- SR 触发器(SR flip-flop)有输入 S(置位)和 R(复位),输出 $Q$ 和 $\overline{Q}$,由两个交叉耦合的 NOR 门构成。
S=1, R=0把 $Q$ 置为 1。S=0, R=1把 $Q$ 复位为 0。S=0, R=0保持当前状态,这就是记忆。S=1, R=1是无效的:它同时要求置位和复位。- JK 触发器(JK flip-flop)给
1,1这个输入赋予了含义,从而消除了那个缺陷:翻转(toggle),输出变成它的反面。这让它非常适合做计数器(counters),因为一串翻转的触发器就是在二进制计数。 - JK 通常是有时钟的:输入只在时钟边沿起作用,这让机器里的每个触发器保持同步。

把无效的输入变成有用的输入
For an SR flip-flop, which statements are correct? Select all · 所有 that apply. · 关于 SR 触发器,哪些说法正确?选出所有适用的。
Toggling on 1,1 is the JK's improvement. On an SR that input asks for set and reset at once and is invalid. · 在 1,1 上翻转是 JK 的改进。在 SR 上那个输入同时要求置位和复位,是无效的。
The JK flip-flop's toggle behaviour is what makes it suitable for building counters. · JK 触发器的翻转行为正是它适合构建计数器的原因。
A chain of flip-flops each toggling on its input counts in binary. Clocking them keeps every stage in step. · 一串各自在输入上翻转的触发器就是在二进制计数。加时钟让每一级保持同步。
Worked example: trace an SR flip-flop
- $Q$ is currently 0. Give $Q$ after the inputs S=1 R=0, then S=0 R=0, then S=0 R=1.
- S=1, R=0 sets the output, so $Q$ becomes 1.
- S=0, R=0 holds, so $Q$ stays 1. This is the step that shows it is a memory: the inputs say nothing, and the output persists.
- S=0, R=1 resets, so $Q$ becomes 0. If S=1 and R=1 were applied, the answer is that the input is invalid, not a value.
例题:追踪一个 SR 触发器
- $Q$ 当前是 0。给出依次施加 S=1 R=0、S=0 R=0、S=0 R=1 之后的 $Q$。
- S=1、R=0 置位输出,所以 $Q$ 变成 1。
- S=0、R=0 保持,所以 $Q$ 仍是 1。正是这一步显示它是记忆:输入什么也没说,输出却留了下来。
- S=0、R=1 复位,所以 $Q$ 变成 0。如果施加 S=1 且 R=1,答案是这个输入无效,而不是某个值。
Marks that slip away
- $S = A \oplus B$ and $C = A \cdot B$: XOR for the sum, AND for the carry. Swapping them loses both marks.
- "Half" means no carry-in, not "half the bits".
- A full adder is two half adders plus an OR, and the OR combines the two carries.
- On an SR flip-flop,
0,0holds and1,1is invalid. The JK's improvement is that1,1toggles.
容易丢掉的分
- $S = A \oplus B$、$C = A \cdot B$:和用 XOR,进位用 AND。互换会丢掉两分。
- "半"意味着没有进位输入,不是"位数减半"。
- 全加器是两个半加器加一个 OR,那个 OR 把两个进位合并。
- 在 SR 触发器上,
0,0保持,1,1无效。JK 的改进是让1,1翻转。
You've got it
- half adder: two bits in, $S = A \oplus B$ from an XOR and $C = A \cdot B$ from an AND; no carry-in
- full adder: three bits in, built from two half adders plus an OR; chain them, carry-out to carry-in, for a ripple-carry adder
- a flip-flop is bistable and stores one bit; $n$ flip-flops make an $n$-bit register, and they are the cells of SRAM
- SR: set, reset,
0,0holds,1,1invalid · JK:1,1toggles, which is what makes counters, and it is clocked to stay synchronised
你掌握了
- 半加器:两位输入,XOR 给出 $S = A \oplus B$,AND 给出 $C = A \cdot B$;没有进位输入
- 全加器:三位输入,由两个半加器加一个 OR 构成;把它们串起来、进位输出接进位输入,就是行波进位加法器
- 触发器是双稳态的,存一位;$n$ 个触发器构成 $n$ 位寄存器,它们也是 SRAM 的单元
- SR:置位、复位,
0,0保持,1,1无效 · JK:1,1翻转,这正是计数器的来源,并且它有时钟以保持同步