| English | 意味 |
|---|---|
| interrupt/ˈɪntərʌpt/ | 割り込み |
| clock speed/klɒk spiːd/ | クロック速度 |
| fetch-execute cycle/fetʃ ˈeksɪkjuːt ˈsaɪkl/ | 取指-実行サイクル |
| cores/kɔːz/ | コア |
| cache/kæʃ/ | キャッシュ |
| word size/wɜːd saɪz/ | ワードサイズ |
| port/pɔːt/ | ポート |
| peripheral/pəˈrɪfərəl/ | 周辺機器 |
| register transfer notation/ˈredʒɪstə ˈtrænsfɜː nəʊˈteɪʃn/ | レジスタ転送記法 |
| stack/stæk/ | スタック |
| interrupt service routine/ˈɪntərʌpt ˈsɜːvɪs ruːˈtiːn/ | 割り込みサービスルーチン |
| interrupt register/ˈɪntərʌpt ˈredʒɪstə/ | 割り込みレジスタ |
Why your laptop drops everything when you press a key
- A processor runs billions of cycles a second. If it had to stop and ask the keyboard "anything yet?" between instructions, it would waste most of them asking.
- Instead the keyboard sends an interrupt 中断. The processor finishes its current instruction, saves its place, deals with the key, and returns as if nothing had happened.
- That one mechanism is how a single processor appears to run your music, your browser and your typing at once.
- This lesson covers what makes a processor fast, how it connects to devices, exactly how it runs one instruction, and how an interrupt cuts in.
What affects performance
- Clock speed 时钟频率: more fetch-execute cycles a second, so more instructions a second, until heat sets the limit.
- Number of cores 核心: each core fetches and executes its own instruction at the same time, so several programs or threads run in parallel. A program must be written to use them, so doubling the cores does not double the speed.
- Bus width: a wider data bus moves more bits per transfer, so fewer transfers; a wider address bus reaches more memory.
- Cache 高速缓存: a small, fast memory next to the processor holding the instructions and data used most recently, so fewer slow trips to RAM. Word size 字长, the amount of RAM and the storage type help too.
CPU パフォーマンスに影響を与える要因をすべて選択してください。
難易度 2/5 · 140 コイン + 今日初回完了時に小ボーナス付与
クロック速度、コア、キャッシュ(およびワードサイズ、RAM、ストレージ、バス幅)はすべてパフォーマンスに影響します。ケースの色は影響しません。
マルチコア CPU は特に以下に役立ちます:
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余分なコアは並列にタスクを実行します。完全にスルースレッドの作業ほど、コアあたりの速度向上から恩恵を受けます。
____ メモリはプロセッサー隣接の小容量・高速記憶装置で、最近使用された指令とデータを保持し、RAM への低速アクセスを減らします。
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キャッシュが多いほど、ワークセットの大部分がプロセッサー隣接に置かれ、これがあらゆるパフォーマンス比較で登場する理由です。
Worked example: "explain why the new computer is faster"
- Compare the two specifications line by line, each with its reason.
- 3.8 GHz against 2.4 GHz: more cycles a second, so more instructions executed a second.
- 8 cores against 4: twice as many instructions can be fetched and executed at the same time, for software that uses them.
- 16 MB of cache against 4 MB: more of the working set is held next to the processor, so fewer waits for RAM. Each line is two marks: the factor and its consequence.
Ports
- A port 端口 is a physical socket that connects a peripheral 外围设备.
- USB (Universal Serial Bus) is general-purpose: keyboards, drives, phones. It is plug-and-play: the computer detects the device, identifies it, loads its driver and can power it, with no restart.
- HDMI (High Definition Multimedia Interface) carries digital video and audio down one cable, so nothing is converted to analogue and the picture is not degraded. VGA (Video Graphics Array) is the older analogue video socket.
各ポートが伝送するものをそれぞれ対応させよ。
難易度 2/5 · 140 コイン + 今日初回完了時に小ボーナス付与
異なる信号には異なるソケットが必要である:HDMIケーブルはUSBポートには差し込めない。
The fetch stage
- Once per instruction the processor runs the fetch-execute cycle 取指-执行周期. Fetch comes first, and the exam wants it in register transfer notation 寄存器传送记法.
MAR ← [PC] the address of the next instruction goes to the MAR
PC ← [PC] + 1 the PC now points to the following instruction
MDR ← [[MAR]] the instruction at that address is read into the MDR
CIR ← [MDR] the instruction is copied into the CIR for decoding
- A read signal travels on the control bus, the address on the address bus, and the instruction comes back on the data bus. The PC is incremented straight after its address is copied, so that a jump executed later can still overwrite it.

PC → MAR → memory → MDR → CIR, with the PC incremented on the way
フェッチ步骤を正しい順序に並べ替えよ。
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PC → MAR、PCのインクリメント、読込み信号、その後命令はMDR → CIRへ移動してデコード準備整う。
PCはフェッチ段階でインクリメントされるため、次のサイクルで次の命令を取得できる。
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PCを早期にインクリメントすることで、この命令が実行される時点ではすでに次の命令を指している(ジャンプによって変更されない限り)。
Decode, execute, repeat
- Decode: the control unit works out from the instruction in the CIR which operation it is and where its operands are.
- Execute: arithmetic and logic go to the ALU with the result in the ACC; a load or store moves data between memory and a register; a jump writes a new address into the PC.
- Then the cycle repeats from
MAR ← [PC]. At the end of every cycle the processor also checks whether an interrupt is waiting.
One LOAD and one ADD walk the registers: fetch, decode, execute, repeat
フェチ・エグゼキューションサイクル
ループ内をタップすると、CPUは毎秒数十億回繰り返します。PC/MAR/MDR/CIRレジスタを使用してフェッチがどのように動作するか、そしてデコードおよび実行が取得したものをどう操作するかを見てください。
Worked example: executing two instructions in notation
- Execute
LDD 200(load the contents of address 200 into the ACC):MAR ← 200, thenMDR ← [[MAR]], thenACC ← [MDR]. - Execute
ADD 201:MAR ← 201,MDR ← [[MAR]],ACC ← [ACC] + [MDR]. - Execute
STO 202:MAR ← 202,MDR ← [ACC],[[MAR]] ← [MDR]. - Every line moves one value between two places. The double brackets always mean "the memory location whose address is in the MAR".
LDD 200を実行するレジスタ転送步骤を正しい順序に並べ替えよ。
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アドレスをMARへ、そのアドレスの contents をMDRへ、さらにアキュムレータへ移す。
Interrupts
- An interrupt is a signal that pauses the normal cycle so the processor can deal with an urgent event.
- Causes: a hardware device (a key pressed, a printer buffer empty, a network packet arriving), a software fault (division by zero, an illegal instruction, arithmetic overflow), the operating system's timer marking the end of a time slice, a power-failure warning.
- Interrupts let the system respond promptly without the processor constantly checking devices, and they are how the operating system multitasks.

The cycle, with the interrupt check at the end of each pass
割り込みとは:
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割り込みはフェッチ・エグゼキューテCycleを一時停止させ、CPUが緊急イベントをサービスした後、再続する。
これらの中で割り込みを引き起こすものはどれか? すべて選択せよ。
難易度 2/5 · 140 コイン + 今日初回完了時に小ボーナス付与
ハードウェアイベント、ソフトウェア故障、OSタイマーはすべて割り込みを発生させる。ループの終了は通常のプログラムフローであり、ジャンプによって処理されるものであり、割り込みではない。
Handling an interrupt
- Finish the current instruction. Save the state: the contents of the PC and the other registers go onto the stack 栈.
- Load the address of the interrupt service routine 中断服务程序 (ISR) into the PC and run it. The ISR handles the event.
- Restore the saved state from the stack and carry on with the interrupted program exactly where it left off.

Save, service, restore, resume
割り込みが発生すると、CPUはまず現在の命令を完了してから:
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PCとレジスタを保存し、割り込みサービスルーチンを実行してから状態を復元し、中断した地点から続ける。
Worked example: the four-mark interrupt answer
- Explain how an interrupt from an input device is detected and handled in the fetch-execute cycle.
- The device sends an interrupt signal that sets a flag in the interrupt register 中断寄存器. The processor checks that register at the end of every cycle, after the current instruction has finished executing.
- If a flag is set and the interrupt has a higher priority than the current task, the PC and the other registers are saved on the stack. The address of the ISR is loaded into the PC and the routine runs.
- When it finishes, the registers are restored from the stack and the interrupted program resumes. Four points, in that order.
プロセッサはフェッチ・エグゼキューテCycleの末尾、現在の命令が完了した後に割り込みの有無を確認する。
難易度 1/5 · 100 コイン + 今日初回完了時に小ボーナス付与
このタイミングこそが、状態をきれいに保存できる理由である:命令が中途半端な状態で残ることはない。
Marks that slip away
- The PC is incremented during the fetch, not after the execute. Put
PC ← [PC] + 1second, straight afterMAR ← [PC]. - Interrupts are checked at the end of a cycle, never in the middle of an instruction.
- The state goes onto the stack and comes back from it. "The CPU stops" or "the program is lost" is wrong: it resumes exactly where it was.
- More cores do not double the speed; the software has to use them. Say so when comparing specifications.
You've got it
- performance: clock speed, cores, bus width, cache (plus word size, RAM, storage), each with its consequence
- ports: USB general-purpose and plug-and-play, HDMI digital video and audio, VGA analogue video
- fetch:
MAR ← [PC],PC ← [PC] + 1,MDR ← [[MAR]],CIR ← [MDR]; then decode, execute, repeat - an interrupt is checked at the end of each cycle: save state on the stack, run the ISR, restore, resume