HDL and verification basics

Từ vựng

English	Ý nghĩa
synthesizable/ˈsɪnθəsaɪzəbl/	Có thể tổng hợp
testbench/ˈtestbentʃ/	Bảng kiểm thử

English

HDL: describe hardware, verify by exhaustion

Synthesizable code becomes gates (assign, always @(*), posedge clk); delays and $display live only in the testbench. Simulation runs time; synthesis makes gates.
The exhaustive loop is the same 8-row check as the Karnaugh route, automated.

{exercise:uni-ee3x-hdl}