Latches and flip-flops
Đã giới thiệu| English | Ý nghĩa |
|---|---|
| latch/lætʃ/ | Khóa |
| excitation table/eksɪˈteɪʃn ˈteɪbl/ | Bảng kích thích |
Edge-triggered memory
- A latch is transparent while enabled; a flip-flop samples only at the clock edge — $Q^{+} = D$ at each edge, nothing between.
- The excitation table runs backwards: D = Q⁺ always; T = 1 exactly on a change; J-K toggle on 11.
D flips at edges reading 1, 0, 1 → Q reads 1, 0, 1; wiggle D between edges and Q never notices. That is the whole latch/flip-flop difference.
{exercise:uni-ee3x-flipflop}
A D flip-flop's D wiggles 1→0→1 between two rising edges. Q does what?
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Edge-triggered means exactly that: Q⁺ = D at each edge only. The latch would follow; the flip-flop holds.
A J-K flip-flop starts at Q = 0 and receives (J,K) = (1,0), (1,1), (0,1), (0,0). Q reads —
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(1,0) sets to 1; (1,1) toggles to 0; (0,1) resets to 0; (0,0) holds - machine-traced 1,0,0,0. The forbidden SR state becomes the useful toggle.
While ENABLE is high, a D latch's output —
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A latch is level-sensitive: transparent for the whole ENABLE-high interval. A flip-flop samples only at the edge - that is the whole distinction.