Latches and flip-flops
Introduced| English | Meaning |
|---|---|
| flip-flop/flɪp flɒp/ | A clocked circuit that stores one bit and changes only at a clock edge. |
| latch/lætʃ/ | A one-bit memory circuit that follows its input while enabled and holds the value otherwise. |
| sequential logic/siːˈkwenʃl ˈlɒdʒɪk/ | Logic whose outputs depend on both present inputs and stored past states. |
| clock edge/klɒk edʒ/ | The rising or falling moment of a clock signal, when flip-flops change state. |
| toggles | toggles |
| excitation table/eksɪˈteɪʃn ˈteɪbl/ | A table that shows the inputs a flip-flop needs for each change from present state to next state. |
The doorbell that remembers
- Press a doorbell with a memory light and the light stays on after your finger leaves. The circuit remembers that something happened.
- So far every output depended only on the present inputs. Memory needs feedback, and this lesson builds it up to the flip-flop in every processor.
Feedback makes a latch
- Sequential logic 时序逻辑 has state: its output depends on what happened before. The simplest memory is a latch 锁存器: two NOR gates, each feeding the other.
- The SR latch remembers which input last pulsed: S (set) makes $Q = 1$, R (reset) makes $Q = 0$, and with both low it holds. $S = R = 1$ is forbidden: both outputs go low, and releasing them together leaves an unpredictable state.
An SR latch has Q = 1. S and R are both low. What is Q?
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With both inputs low the cross-coupled gates keep each other in place, which is exactly the memory. Only S = R = 1 is forbidden.
The D latch is transparent
- A D latch adds an ENABLE input. While ENABLE is high, $Q$ follows $D$ continuously; when ENABLE falls, $Q$ freezes at its last value.
- "Transparent for a whole level" is the problem. If $D$ wiggles while ENABLE is high, every wiggle passes straight through.
While ENABLE is high, a D latch's output —
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A latch is level-sensitive: transparent for the whole time ENABLE is high. A flip-flop samples only at the edge; that is the whole distinction.
The flip-flop samples at an edge
- A flip-flop 触发器 is edge-triggered. The D flip-flop samples $D$ only at the clock edge 时钟边沿 (usually rising) and holds it until the next edge.
- $Q$ after the edge equals $D$ just before it: $Q^{+} = D$. Between edges, $D$ can change freely and nothing happens.
$D$ reads 1, 0, 1 at three rising edges, and wiggles in between. $Q$ reads 1, 0, 1: one change per edge, none between.
A D flip-flop's D wiggles 1→0→1 between two rising edges. Q does what?
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Edge-triggered means exactly that: $Q^{+} = D$ at each edge only. A latch would follow; the flip-flop holds.
Match each element to its behaviour.
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Level-sensitive latches and edge-triggered flip-flops store the same bit; they differ in when they listen.
The J-K flip-flop toggles
- The J-K flip-flop turns the forbidden SR input into a useful one. $J$ sets, $K$ resets, $J = K = 0$ holds, and $J = K = 1$ toggles 翻转: $Q^{+} = Q'$.
- From $Q = 0$, the inputs $(J, K) = (1,0), (1,1), (0,1), (0,0)$ give set, toggle, reset, hold: $Q$ reads 1, 0, 0, 0.
A J-K flip-flop starts at Q = 0 and receives (J,K) = (1,0), (1,1), (0,1), (0,0). Q reads —
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(1,0) sets to 1; (1,1) toggles to 0; (0,1) resets to 0; (0,0) holds. The forbidden SR input has become the useful toggle.
A J-K flip-flop with J = K = 1 starts at Q = 0. How many of the next 7 clock edges leave Q = 1?
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It toggles every edge: 1, 0, 1, 0, 1, 0, 1. Edges 1, 3, 5 and 7 leave $Q = 1$. The output is the clock frequency divided by 2.
The excitation table runs backwards
- To design with flip-flops, start from the transition you need, $Q \to Q^{+}$, and ask which inputs produce it. That list is the excitation table 激励表.
- For D it is simply $D = Q^{+}$. For J-K: $0 \to 0$ needs $J = 0$ ($K$ either); $0 \to 1$ needs $J = 1$; $1 \to 0$ needs $K = 1$; $1 \to 1$ needs $K = 0$.
To take a J-K flip-flop from Q = 0 to Q = 1, K may be either 0 or 1, as long as J = 1.
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$J = 1, K = 0$ sets and $J = 1, K = 1$ toggles from 0: both give 1, so K is a don't-care. Those don't-cares make J-K next-state logic small.
Three common slips
- The wrong edge. Rising or falling is part of the specification; read it.
- Latch for flip-flop. A latch is transparent for a whole level; a flip-flop samples at one instant.
- Expecting Q to follow D at once. $Q$ waits for the edge.
Recap
- Latches are level-sensitive; flip-flops are edge-triggered with $Q^{+} = D$.
- J-K: set, reset, hold, and toggle on $J = K = 1$.
- The excitation table turns a wanted transition into the required inputs.