The CPU and the fetch-execute cycle
The central processing unit
- The CPU processes data and carries out instructions, repeating a cycle millions of times a second.
- Inside are the ALU, control unit and registers, linked by buses.
- It runs every program through the fetch–execute cycle.
Parts of the CPU
- ALU — does calculations and logical comparisons.
- Control unit (CU) — sends control signals to manage all the parts.
- Registers — tiny, very fast stores holding one value each.
- Three buses link them to memory: address (one way), data (both ways), control.
Practice
The ALU in a CPU:
The arithmetic logic unit does the maths and logic; the control unit manages the parts.
Registers and the fetch–execute cycle
- Special registers: PC (address of the next instruction), MAR (address to access), MDR (data/instruction fetched), CIR (instruction being run), ACC (the ALU's result).
- The cycle repeats three stages: Fetch (copy the instruction into the CPU, then PC + 1) → Decode (the CU works out what it means) → Execute (carry it out).
Practice
The program counter (PC) holds:
The PC holds the next instruction's address; the CIR holds the current instruction; the ACC holds results.
Practice
Put the stages of the cycle in order.
Fetch the instruction, decode what it means, then execute it — repeated continuously.
Cache, performance, embedded systems
- Cache is a small amount of very fast memory near the CPU, holding often-used data — so the CPU waits less.
- Performance depends on the number of cores, the cache size, and the clock speed (cycles per second).
- An embedded system is a small computer built into a device for one fixed job (washing machine, microwave).
Practice
Which change would improve CPU performance?
More cores, a larger cache and a higher clock speed all improve performance.
Practice
Cache memory speeds up the computer because it:
The CPU reads from cache far faster than from main memory, so it waits less.
You've got it
Key idea
- CPU = ALU (maths/logic) + CU (control signals) + registers, linked by address/data/control buses
- key registers: PC (next instruction), MAR/MDR (memory), CIR (current), ACC (result)
- the cycle: fetch → decode → execute
- performance: cores, cache size, clock speed; cache = fast memory near the CPU