ADC, DAC and sensors
Đã giới thiệu| English | Ý nghĩa |
|---|---|
| ADC/ˌeɪ diː ˈsiː/ | ADC |
| resolution/ˌrezəˈluːʃn/ | độ phân giải |
| LSB | bit có ý nghĩa thấp nhất |
| DAC/ˌdiː eɪ ˈsiː/ | DAC |
| sample-and-hold | sample-and-hold |
The staircase
- An ADC quantises: an N-bit converter over $V_{ref}$ has a resolution of one LSB $= V_{ref}/2^{N}$. Each code owns a one-LSB band of input voltage.
- The requirement picks N: to resolve 0.1 °C from a 10 mV/°C sensor you need 1 mV — 12-bit (0.806 mV) passes, 10-bit (3.22 mV) fails.
$V_{ref} = 3.3$ V, 12 bits: one LSB = 3.3/4096 = 0.806 mV; 1.65 V reads exactly 2048 — mid-scale ✓. A DAC walks the staircase in reverse: writing 2048 gives 1.650 V.
{exercise:uni-ee0861-lsb}
A 10-bit ADC with V_ref = 3.3 V resolves —
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3.3/2^10 = 3.3/1024 = 3.22 mV. The 0.806 mV figure belongs to 12 bits — resolution is only meaningful with both N and V_ref.
The impedance trap
- The sample-and-hold capacitor ($\approx$ 7 pF) charges through the source; settling to ½ LSB needs $t_{s} \ge R C \ln(2^{N+1})$: 50 kΩ wants 3.2 µs, a 1 µs window allows only 16 kΩ.
- Averaging 16 noisy samples buys about 2 effective bits — it cannot repair a systematic offset.
{exercise:uni-ee0862-rc}
For a 50 kΩ source and 7 pF sampling cap, settling to ½ LSB at 12 bits needs about —
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R·C·ln(2^13) = 50e3 × 7e-12 × 9.01 ≈ 3.2 µs. The datasheet 50 kΩ figure presumes exactly this sampling window.
Averaging 16 samples of white noise gains about —
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Noise falls as sqrt(16) = 4×, which is 2 bits — but a systematic offset or a drooped sample survives averaging untouched.