Memory and I/O
Đã giới thiệu| English | Ý nghĩa |
|---|---|
| memory-mapped I/O | memory-mapped I/O |
| GPIO | GPIO |
| polling | khám phá |
Peripherals are memory
- Memory-mapped I/O makes a peripheral register look exactly like a memory location: reading a data register receives; writing one sends.
- A GPIO port has two registers — direction (one bit per pin: input or output) and data (the pin's level). Configure once, then read or write forever.
{exercise:uni-ee0831-gpio}
A pin stays an input no matter what you write to the data register. The likely cause is —
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Direction decides which way the pin speaks; data only carries what it says. Configure direction first, always.
The price of polling
- Polling reads a status bit in a loop. At 84 MHz with a 4-cycle lap, the CPU does 21 million laps per second; waiting 1 ms burns ~21 000 laps = 84 000 cycles — 100% of the CPU.
- Every polled wait should carry a timeout: a dead sensor must not hang the product.
{exercise:uni-ee0832-poll}
A 4-cycle polling loop at 84 MHz waits 1 ms. The CPU cycles burned are about —
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84e6 cycles/s ÷ 4 per lap = 21e6 laps/s; 1 ms = 21 000 laps × 4 = 84 000 cycles — 100% of that millisecond.
The one safeguard every polling loop must carry is —
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A timeout bounds the wait: a dead sensor returns an error instead of hanging the product. The watchdog is the outer net, not the loop guard.