Microcontroller architecture
Đã giới thiệu| English | Ý nghĩa |
|---|---|
| microcontroller | vi điều khiển |
| fetch-decode-execute cycle | fetch-decode-execute cycle |
| program counter/ˈprəʊɡræm ˈkaʊntə/ | bộ đếm chương trình |
| bus/bʌs/ | bus |
| clock/klɒk/ | đồng hồ |
One chip, one loop
- A microcontroller holds flash, SRAM and a CPU on one die. The CPU runs the fetch-decode-execute cycle: the program counter names the next instruction, the control unit decodes it, the datapath executes, the PC advances.
- Every transfer rides the bus — address lines say where, data lines carry what — sequenced by the clock at 84 MHz.
64 KB flash needs $2^{16}$ → 16 address lines, sitting at 0x0000_0000–0x0000_FFFF; 8 KB SRAM needs 13, at 0x2000_0000–0x2000_1FFF. Regions whose top bits differ can never overlap ✓.
{exercise:uni-ee0811-map}
A chip maps 32 KB of flash. How many address lines does it need?
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32 KB = 2^15 bytes, so 15 address lines select any byte. 32 confuses KB with lines; 5 reads 32 as a count, not a size.
Flash at 0x0000_0000 and SRAM at 0x2000_0000 can never overlap because —
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The address decoder looks at bits [31:16]: 0x0000 selects flash, 0x2000 selects SRAM — no address can satisfy both.
Instruction budget
- One instruction $\approx$ 11.9 ns at 84 MHz. A 100-instruction control pass costs 1.19 µs; a 1 ms loop has room for about 840 passes.
- This budget arithmetic returns in every later unit: polling, interrupts, serial — all priced against it.
{exercise:uni-ee0812-budget}
At 84 MHz, a 250-instruction control pass takes about —
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250 × 11.9 ns ≈ 3.0 µs. The instruction budget prices any pass before it runs.