HDL and verification basics
Introduzido| English | Significado |
|---|---|
| simulation/ˌsɪmjʊˈleɪʃn/ | Running a model of a circuit on a computer to predict how it will behave. |
| hardware description language/ˈhɑːdweə dɪˈskrɪpʃn ˈlæŋɡwɪdʒ/ | A language such as Verilog or VHDL used to describe and simulate digital circuits. |
| synthesizable/ˈsɪnθəsaɪzəbl/ | sintetizável |
| testbench/ˈtestbentʃ/ | plataforma de teste |
64 gates, 64 chances to slip
- Wire 64 gates by hand and each connection is a chance for a mistake. Modern chips have billions.
- Industry does not answer this with more careful drawing. It describes the hardware in a language and proves the description with simulation.
Describe hardware in code
- A hardware description language 硬件描述语言 (HDL) such as Verilog or VHDL describes what a circuit is and how it behaves. A synthesis tool turns it into gates.
- Only synthesizable 可综合 code can become hardware: continuous
assign,always @(*)blocks andalways @(posedge clk)registers.
Any Verilog that simulates correctly can be turned into gates.
Dificuldade 1/5 · Moedas 100 + pequeno bônus na primeira conclusão hoje
Simulation accepts constructs with no hardware meaning, such as delays and $display. Only the synthesizable subset becomes gates.
A full adder in four lines
- The module lists its ports, then states the two output equations from the earlier lesson.
module full_adder(input a, b, cin,
output sum, cout);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
^is XOR,&is AND,|is OR. Everyassignruns all the time, in parallel, like the wires it stands for.
Match each Verilog operator to its gate.
Dificuldade 2/5 · Moedas 140 + pequeno bônus na primeira conclusão hoje
These bitwise operators map one-to-one onto gates, which is why assign lines read like a schematic.
The testbench checks it
- A testbench 测试平台 is code that drives inputs into the module and checks the outputs. It runs only in simulation 仿真 and never becomes hardware.
- It may use things hardware cannot: delays such as
#10, loops over test cases, and$displayto print results.
Which construct belongs ONLY in a testbench?
Dificuldade 1/5 · Moedas 100 + pequeno bônus na primeira conclusão hoje
Delays simulate but do not synthesise: hardware has no #10. The other three all become gates or flip-flops.
Worked example: an independent check
- The testbench drives all 8 combinations of
a,b,cinand checks $a + b + c_{in} = 2 \cdot c_{out} + s$ each time. All 8 pass. - The check uses arithmetic, not a second gate description. A copy of the design would repeat any mistake in it, so it would prove nothing.
An exhaustive testbench for a block with 5 one-bit inputs must try how many input combinations?
Dificuldade 2/5 · Moedas 140 + pequeno bônus na primeira conclusão hoje
$2^{5} = 32$. Small blocks are cheap to check completely; a 64-bit adder is not, which is why big designs mix exhaustive checks of parts with random tests.
A testbench that checks a full adder against a second gate copy of the same design is —
Dificuldade 1/5 · Moedas 100 + pequeno bônus na primeira conclusão hoje
The reference must be independent: arithmetic ($a + b + c_{in} = 2c_{out} + s$) or a hand trace. A restated implementation repeats the very bug you are looking for.
Worked example: a shift register
- A 4-bit serial-in shift register is one clocked line. The concatenation
{q[2:0], sin}drops the top bit and putssinin at the right.
module shift4(input clk, sin,
output reg [3:0] q);
always @(posedge clk)
q <= {q[2:0], sin};
endmodule
- From 0000 with
sin= 1, 0, 1, 1, simulation shows q = 0001, 0010, 0101, 1011.
The 4-bit shift register q <= {q[2:0], sin}, starting at 0000, with sin = 1, 0, 1, 1 over four clocks traces q as —
Dificuldade 1/5 · Moedas 100 + pequeno bônus na primeira conclusão hoje
Each edge shifts left and admits sin on the right, giving 0001, 0010, 0101, 1011. The concatenation is the shift.
Three common slips
- A testbench that restates the design. It checks the code against itself; use arithmetic or a hand trace.
- Testbench constructs in a hardware module. Delays and
$displaydo not synthesise. - No reset. A register without one starts in an unknown state in hardware, even if simulation looks fine.
A counter module has no reset. In simulation every register starts at x (unknown). What does that tell you?
Dificuldade 1/5 · Moedas 100 + pequeno bônus na primeira conclusão hoje
Real flip-flops power up at random values. The x in simulation is a warning, not a simulator fault; a reset puts the counter in a known state.
Recap
- Synthesizable modules become gates; testbenches only simulate.
- Check against an independent reference: arithmetic or a traced sequence.
- Small input spaces are checked exhaustively; ship each module with its testbench.