Digital control: what a sample costs
Introduced| English | Meaning |
|---|---|
| phase margin | How much extra phase lag at the gain crossover frequency would make a feedback loop unstable. |
| ADC/ˌeɪ diː ˈsiː/ | An analogue-to-digital converter: it samples a voltage and turns it into a number. |
| zero-order hold | A converter that holds each sample's value constant until the next sample. |
| aliasing/ˈeɪlɪəsɪŋ/ | When a signal is sampled too slowly, so high frequencies appear as false lower frequencies. |
| Nyquist frequency | Half the sampling frequency, the highest frequency a sampled signal can represent. |
| bandwidth/ˈbændwɪdθ/ | The frequency range carried by a signal or channel; in networking, often used for its data transfer capacity. |
The loop runs on a microcontroller
- The controller runs in discrete time. Sampling, word length and computation time each cost phase margin, affordable only if they are counted.
- An ADC samples every $T$ seconds; a zero-order hold keeps the output constant until the next sample. On average that is a delay of $T/2$, costing $\omega T/2$ of phase.
Tustin and aliasing
- Tustin replaces $s$ by $\tfrac{2}{T}\tfrac{z - 1}{z + 1}$; for the integral this is the trapezium rule, $I_k = I_{k-1} + \tfrac T2(e_k + e_{k-1})$.
- Anything above the Nyquist frequency, half the sample rate, folds back into the band, so filter it out before the ADC.
Which digital cost?
Name the digital effect behind each number.
Nyquist frequency at a 1 kHz sample rate (Hz)?
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Half the sample rate.
The anti-alias filter goes:
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Once sampled, an alias cannot be separated.
Choosing the sample rate
- At 74.4 rad/s the hold costs $74.4T/2$: $\mathbf{2.1°}$ at 1 kHz but $\mathbf{21°}$ at 100 Hz.
- The phase margin falls from 65.2° to 63.8° at 1 kHz, but to 51.3° at 100 Hz.
- Choose 1 kHz: about 85 samples per cycle of the 11.8 Hz bandwidth.
Hold phase at 74.4 rad/s, T = 1 ms (one decimal, degrees)?
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omega T / 2 in degrees.
At T = 10 ms (degrees, whole number)?
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Ten times larger.
Quantisation and latency
- The encoder gives 100 000 counts per valve turn: $\mathbf{0.0036°}$ per count, far below the 0.5° spec.
- Speed from counting at 1 kHz resolves only $\mathbf{3.14}$ rad/s at the motor, one more reason to avoid derivative action. A 0.2 ms computation delay adds 0.6° of lag.
Degrees per count with 100 000 counts per turn (four decimals)?
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360 over 100 000.
A computation delay costs phase margin.
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0.6 degrees for 0.2 ms at crossover.
The integral in code
- Tustin's integral at $T = 1$ ms is one line per sample: $I_k = I_{k-1} + 0.4965(e_k + e_{k-1})$, since $K_iT/2 = 993 \times 0.0005$. Then $u_k = 134e_k + I_k$, clamped to ±12 V.
- The clamp sits inside the loop: if $u_k$ saturates, do not store the new $I_k$. That is anti-windup in two lines of code.
Tustin integral with $K_i = 993$ and $T = 1$ ms: the coefficient on $(e_k + e_{k-1})$ (four decimals)?
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$K_iT/2 = 993 \times 0.0005 = 0.4965$.
Worked example: mains hum in the temperature
- Sample the tank temperature at 10 Hz. 50 Hz pickup on the sensor wires is exactly five times the sample rate, so every sample catches the hum at the same phase: it aliases to 0 Hz and looks like a constant offset.
- No later filter can remove it. An RC filter at 1 Hz before the ADC passes the slow temperature and cuts 50 Hz to $1/\sqrt{1 + 50^2} = \mathbf{0.020}$, 2% of its size.
First-order filter with a 1 Hz corner: gain at 50 Hz (three decimals)?
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$1/\sqrt{1 + (50/1)^2} = 0.020$.
Hum aliased into the band can be filtered out digitally after sampling.
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Once aliased it sits at the same frequency as the real signal; the filter must act before the ADC.
Three digital slips
- No anti-alias filter. High frequencies fold into the band.
- Computation delay ignored. It costs phase like the hold.
- Differentiating a quantised position. The steps become noise.
Recap
- The hold costs $\omega T/2$: 2.1° at 1 kHz, 21° at 100 Hz.
- Sample 20 to 30 times the bandwidth or more; Tustin for the controller.
- 0.0036° per count; 3.14 rad/s speed resolution; 0.6° for 0.2 ms delay.