Instruction set architecture
도입됨
어휘
| English | 의미 |
|---|---|
| computer architecture | The machine below the program. |
| instruction set architecture | instruction set architecture |
| RISC/rɪsk/ | RISC |
| load-store | load-store |
| byte-addressable | byte-addressable |
English
The contract
- Computer architecture is the machine below the program. The instruction set architecture (ISA) is its contract with software: everything a compiler may rely on, nothing about the wires. Two machines with one ISA run the same binaries.
- Our teaching ISA is RISC in spirit: fixed 32-bit instructions, load-store (only
lw/swtouch memory), 16 registers with R0 hardwired to zero.
Example
R-type: opcode(4) | rd(4) | rs(4) | rt(4) | shift(4) | funct(8) — 28 bits used, zero-padded to 32. I-type: opcode(4) | rt(4) | rs(4) | immediate(16).
{exercise:uni-cs0601-isa}
연습
The ISA is best described as —
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It states everything software may rely on and nothing about implementation.
English
Encode and decode
- Encode
add R3, R1, R2with opcode 1: fields $0001\,0011\,0001\,0010\,0000\,00000001$. Decode opcode 2, rt 4, rs 1, immediate $127$:addi R4, R1, 127. - A 16-bit two's complement immediate spans $-32\,768$ to $32\,767$;
addi R2, R0, 40000cannot encode and needs two instructions.
{exercise:uni-cs0601-encode}
연습
A 16-bit signed immediate can hold —
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The range is −32 768 to 32 767; 40 000 needs two instructions.
English
What R0 buys
- With byte-addressable memory and 32-bit words,
lwoffsets are multiples of 4 — a 16-bit offset reaches $2^{16}$ bytes = 64 KiB from the base register. addi R0, R0, 0is the canonical no-op;add R5, R0, R0zeroes R5 in one cycle;beq R1, R0, loopcompares to zero with no constant operand — a dedicated zero register removes a whole class of move instructions.
{exercise:uni-cs0601-zero}
연습
R0 hardwired to zero lets a program —
난이도 1/5 · 100코인 + 오늘 첫 완료 시 작은 보너스 추가
add R5, R0, R0 zeroes R5 in one cycle — no move-immediate needed.