Debugging and integration
導入済み| English | 意味 |
|---|---|
| watchdog | ウォッチドッグ |
| debounce | デバウンス |
"It froze twice last night"
- Every firmware bug arrives as a rumour. Firmware is tested on the exact hardware it ships on, and the fault rarely appears when someone is watching.
- Method is the difference between fixing a bug and only moving it. This lesson gives that method.
The debug loop
- Reproduce the fault with the smallest input. Isolate it at a boundary with an LED, a breakpoint or one UART print.
- Fix one thing, then re-verify. Two changes at once leave you unsure which one helped.
Put the debug loop in order.
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Without a reproduction you cannot tell whether a fix worked; fixing more than one thing hides which one did.
Bisection
- Put a probe in the middle of the suspect code. Whether the probe fires before the fault tells you which half holds the bug.
- Each probe halves the range, so $\log_{2}(n)$ probes find one instruction among $n$: ten for 1024.
Bisection searches 512 suspect instructions. How many probes does it need at most?
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Each probe halves the range: $\log_{2} 512 = 9$.
A suspect region holds 4096 instructions. How many bisection runs find the faulty one?
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$2^{12} = 4096$, so 12 runs. Doubling the code adds only one run.
The watchdog
- A watchdog 看门狗 is a counter that resets the chip if it runs out. The firmware must "kick" it (restart the count) regularly.
- A hung system then reboots by design instead of freezing. Kick it only from the main loop, never from an ISR.
Why is it wrong to kick the watchdog inside an ISR?
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If an ISR kicks the watchdog, the main loop can hang while the interrupts keep it fed, and the reset never comes.
Debounce
- A pressed button bounces: its contact opens and closes for a few milliseconds. Debounce 消抖 accepts a new state only after N equal readings in a row.
- It combines a timer tick, a GPIO read and a state decision: the whole course in one routine.
Worked example: a debounce trace
- Samples every 10 ms read 1, 0, 0, 1. Rule: two equal readings in a row.
- At 10 ms there is one 0; at 20 ms a second 0, so a stable 0 is declared. The 1 at 30 ms is a single sample and is ignored.
Samples 1, 0, 0, 1 arrive every 10 ms, starting at 0 ms. With a two-in-a-row rule, when is a stable state declared?
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At 10 ms there is one 0 and no verdict; at 20 ms the second 0 makes a stable 0. The 1 at 30 ms is a single sample.
The rule needs three equal readings in a row, sampled every 5 ms from 0 ms. The readings are 0, 1, 0, 1, 1, 1. At what time, in ms, is a stable 1 declared?
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The 1s at 15, 20 and 25 ms are the first three in a row, so the verdict comes at 25 ms.
Worked example: bisecting the freeze
- The suspect region is 1024 instructions. Make instruction 512 light the LED: dark at the freeze means the first half; lit means the second.
- Each run halves the region: 512, 256, 128 … after ten runs, one instruction is left, because $2^{10} = 1024$.
Three common slips
- Fixing two things at once. One helps, one breaks something else, and now there are three bugs.
- Testing on another board. Debug on the same board revision that failed.
- Turning off the watchdog "for now". The field failure it would have survived is exactly the one that ships.
While debugging, it is good practice to switch off the watchdog and leave it off once the bug is fixed.
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A product shipped without its watchdog freezes in the field instead of rebooting. If it must be off for a session, turn it back on before release.
Recap
- Reproduce, bisect, fix one thing, re-verify.
- $\log_{2}(n)$ probes find the fault among $n$ instructions.
- Debounce needs N equal readings in a row; kick the watchdog from the main loop only.