Machine instructions
導入済み| English | 意味 |
|---|---|
| immediate | immediate |
| addressing mode/əˈdresɪŋ məʊd/ | The rule an instruction uses to specify where an operand is or how its address is obtained. |
| RISC/rɪsk/ | Reduced instruction set computer: an instruction-set design approach emphasising comparatively simple operations. |
| CISC/sɪsk/ | CISC |
One line of C, several machine steps
- The line
a[i] = a[i] + 1looks like one action. The processor carries it out as a short list of tiny instructions. - Every compiler targets this small vocabulary, and every speed question ends here. This lesson reads it.
The instruction kinds
add rd, rs1, rs2adds two registers;addiadds an immediate 立即数, a constant written inside the instruction.lw(load word) andsw(store word) move data between memory and registers;beqandbnecompare two registers and branch.
Match each instruction to what it does.
難易度 2/5 · 140 コイン + 今日初回達成時の小ボーナス
Four instruction kinds cover arithmetic, memory and control.
Addressing modes
- The addressing mode 寻址方式 says where an operand lives: in a register, in the instruction (immediate), or in memory at base + offset.
lw R1, 8(R2)reads memory at address R2 + 8. The 8 is an offset, not the value 8.
In lw R1, 0(R2) the 0 is —
難易度 1/5 · 100 コイン + 今日初回達成時の小ボーナス
Address = R2 + 0. This is base + offset addressing.
R2 holds 400. Which memory address does lw R1, 12(R2) read?
難易度 2/5 · 140 コイン + 今日初回達成時の小ボーナス
Base + offset = 400 + 12 = 412.
Why RISC only loads and stores
- In RISC 精简指令集 designs, only
lwandswtouch memory; arithmetic works register to register. One simple shape decodes fast and fits a pipeline well. - CISC 复杂指令集 designs let arithmetic read memory directly. The code is shorter but harder to pipeline: more instructions against faster instructions.
In a RISC load/store design, add can take one of its inputs straight from memory.
難易度 1/5 · 100 コイン + 今日初回達成時の小ボーナス
Only lw and sw touch memory. add works on registers only.
A loop is two instructions
loop: addi R1, R1, -1thenbne R1, R0, loop. R0 always holds 0, so this means "subtract 1, and jump back unless R1 is now 0".- A C
whileloop becomes exactly this pair plus the body.
A C while loop that counts down compiles to the pair —
難易度 1/5 · 100 コイン + 今日初回達成時の小ボーナス
Two instructions per pass — decrement, compare with zero, jump back.
R1 starts at 6. The loop is addi R1, R1, -1 then bne R1, R0, loop. How many times does bne jump back?
難易度 2/5 · 140 コイン + 今日初回達成時の小ボーナス
The body runs 6 times. After the sixth pass R1 is 0, so the last bne falls through; it jumps back 5 times.
Arrays are address arithmetic
- Element
a[i]lives at base + $i$ × element size. With 4-byte words,a[5]is at base + 20. - So a pointer is just a base register, and indexing is a multiply and an add.
An array of 4-byte integers starts at address 2000. At which address is a[7]?
難易度 2/5 · 140 コイン + 今日初回達成時の小ボーナス
2000 + 7 × 4 = 2028.
Worked example: a[i] = a[i] + 1
- Base address in R2, $i = 3$, 4-byte words: the offset is $3 \times 4 = 12$, so the element is at R2 + 12.
lw R5, 12(R2)loads it;addi R5, R5, 1adds one;sw R5, 12(R2)stores it back: load, add, store.
Put the machine steps of a[i] = a[i] + 1 in order.
難易度 3/5 · 200 コイン + 今日初回達成時の小ボーナス
Address, load, add, store — indexing is scaled address arithmetic.
Worked example: counting a loop
- R1 starts at 3. Pass 1: R1 becomes 2,
bnejumps back. Pass 2: R1 becomes 1, jumps back. Pass 3: R1 becomes 0, falls through. - The body runs 3 times and
bnejumps back only twice.
Three common slips
- Reading
0(R2)as the value 0. It is offset 0 from the address in R2. - Forgetting to set the loop counter. The loop then runs from whatever R1 held.
- Using $i$ as the byte offset. Scale it by the element size: $4i$ for 4-byte words.
Recap
- add, addi, lw, sw, beq and bne; memory only through load and store, at base + offset.
- RISC trades more instructions for simpler, faster ones that pipeline well.
- A while loop is decrement and branch;
a[i]is base + $i$ × size.