Registers, counters and memory
Diperkenalkan| English | Makna |
|---|---|
| register/ˈredʒɪstə/ | register |
| shift register/ʃɪft ˈredʒɪstə/ | shift register |
| memory/ˈmeməri/ | memori |
| synchronous counter/ˈsɪŋkrənəs ˈkaʊntə/ | A counter in which every flip-flop is clocked by the same clock signal. |
| ripple counter/ˈrɪpl ˈkaʊntə/ | A counter in which each flip-flop is clocked by the output of the one before it. |
| address lines | address lines |
7, then 8
- A scoreboard changes from 7 to 8 while every other digit stays still. That is a register updating, and counting is a register that updates itself.
- This lesson builds the storage blocks of a computer: registers, shift registers, counters and memory.
Registers load n bits together
- A register 寄存器 is a row of D flip-flops sharing one clock. At each edge all $n$ bits load at once; between edges they hold.
- A load-enable input chooses, for each edge, whether to take new data or keep the old. That is how one digit changes while the rest stand still.
In a register with load-enable low, the stored bits follow the data inputs at each clock edge.
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With load-enable low each flip-flop is fed its own output, so it keeps its value. Only an enabled edge loads new data.
Shift registers move bits along
- In a shift register 移位寄存器 each flip-flop's output feeds the next one's input, so the stored bits move one place per clock.
- Serial in, parallel out turns a bit stream into a word; parallel in, serial out does the reverse. Shifting right with inputs 1, 1, 0, 1 gives 1000, 1100, 0110, 1011.
A 4-bit right-shift register starts at 0000. Inputs 1, 0, 0, 1 enter at the left over four clocks. What does it hold?
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Trace: 1000, 0100, 0010, 1001. The first bit in has moved furthest right.
Ripple and synchronous counters
- A ripple counter 异步计数器 chains toggle flip-flops: each output clocks the next. It is simple, but each stage adds its delay, so the top bit settles late.
- A synchronous counter 同步计数器 clocks every flip-flop from the same edge and computes which bits toggle with logic. Every bit changes together.
In a synchronous counter all the flip-flops receive the same clock edge.
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That is the definition. Logic decides which bits toggle, so all bits change together and no delay accumulates, unlike a ripple counter.
Worked example: the 3-bit up-counter
- Bit 0 toggles every clock; bit 1 when $Q_{0} = 1$; bit 2 when $Q_{1} Q_{0} = 11$. A bit toggles when every bit below it is 1, which is how adding 1 carries.
- After reset it counts 000, 001, …, 111 and rolls over to 000: $2^{3} = 8$ states.
In a 3-bit synchronous up-counter, bit 2 toggles when —
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Bit k toggles when all lower bits are 1, which is when they roll over. The count 000 … 111 with $2^{3} = 8$ states is the check.
Worked example: a mod-6 counter
- A mod-6 counter runs 000 to 101 and then back to 000. The codes 110 and 111 must never appear.
- $Q_{2} Q_{1} = 11$ in both unused codes and in no legal count. So $Q_{2} \cdot Q_{1}$ is the clear condition, or 000 is written into the next-state logic for those codes.
A mod-6 counter must return to 000 from 101. The cleanest reset condition is —
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Legal counts 000 to 101 never have $Q_{2} = Q_{1} = 1$, so $Q_{2} \cdot Q_{1}$ picks out exactly the unused codes and clears to 000. $Q_{2}$ alone would also clear 100 and 101.
A mod-10 counter is built from binary flip-flops. How many of its codes are unused?
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Ten states need 4 flip-flops ($2^{4} = 16$), leaving $16 - 10 = 6$ unused codes: 1010 to 1111.
Memory: words and address lines
- Memory 存储器 is an array of words. With $k$ address lines 地址线, it selects one of $2^{k}$ words, each $m$ bits wide.
- An 8K × 8 memory holds $8192 = 2^{13}$ words of 8 bits: 13 address lines and 8 data lines.
An 8K × 8 memory needs how many address lines?
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$k$ address bits select one of $2^{k}$ words: $8192 = 2^{13}$, so 13 lines. The 8 is the word width (data lines), not the address.
Three common slips
- Trusting a ripple counter at speed. It looks fine slowly and fails at the specified clock, because the delays add up.
- Ignoring unused states. A mod-N counter must recover from an illegal code after power-up or noise.
- Mixing up address and data width. In 8K × 8, the 8K sets the address lines and the 8 is the word size.
Recap
- Registers load on a shared edge; shift registers move bits one place per clock.
- Synchronous counters toggle a bit when all lower bits are 1; mod-N counters must handle unused codes.
- $k$ address lines select $2^{k}$ words.