Datapath and control
Introduit| English | Sens |
|---|---|
| datapath | Processor components and connections that store, carry and operate on instruction data. |
| ALU/ˌeɪ el ˈjuː/ | The part of a processor that performs arithmetic and logical operations. |
| control/kənˈtrəʊl/ | The switch settings per instruction: RegWrite, MemRead, MemWrite, MemToReg, ALUSrc, Branch — pure combinational logic on opcode and funct. |
One clock, one instruction
- The datapath is the plumbing: PC feeds instruction memory, the register file reads two sources, the ALU computes, data memory reads or writes, the result writes back, and the PC takes PC + 4 or a branch target.
- Control is the switch settings per instruction: RegWrite, MemRead, MemWrite, MemToReg, ALUSrc, Branch — pure combinational logic on opcode and funct.

{exercise:uni-cs0602-path}
The single-cycle clock must wait for —
Difficulté 1/5 · 100 pièces + un petit bonus lors de la première réussite aujourd'hui
All work fits in one clock, so lw (IM+RF+ALU+DM+wiring = 900 ps) sets the cycle.
The cycle is the slowest citizen
- All work fits in one clock, so the clock waits for the longest instruction:
lw's path. With our parameters (IM 200, RF 100, ALU 200, DM 250, wiring 150 ps): $200 + 100 + 200 + 250 + 150 = 900$ ps per cycle. - 100 instructions take $90\,000$ ps. Speeding up
addwould not help — the machine runs at its slowest instruction's pace.
{exercise:uni-cs0602-cycle}
With IM 200, RF 100, ALU 200, DM 250, wiring 150 ps, the lw cycle is —
Difficulté 1/5 · 100 pièces + un petit bonus lors de la première réussite aujourd'hui
200+100+200+250+150 = 900 ps — the slowest citizen.
Six bits per instruction
lw R4, 8(R1): RegWrite 1, MemRead 1, MemToReg 1, ALUSrc 1 (immediate to ALU), Branch 0, MemWrite 0.sw R5, 12(R1): RegWrite 0, MemWrite 1, MemRead 0, MemToReg = x — a don't care: nothing writes back, so the bit changes nothing observable. Don't-cares are the designer's freedom.
{exercise:uni-cs0602-signals}
For lw, the ALUSrc control bit selects —
Difficulté 1/5 · 100 pièces + un petit bonus lors de la première réussite aujourd'hui
The ALU must add base + immediate, so ALUSrc = 1 routes the immediate.