处理器与内存概览
引入| English | 释义 | 拼音 |
|---|---|---|
| fetch-decode-execute cycle | 取指-译码-执行周期 | qǔ zhǐ - yì mǎ - zhí xíng zhōu qī |
| program counter/ˈprəʊɡræm ˈkaʊntə/ | 程序计数器 | chéng xù jì shù qì |
| instruction register | 指令寄存器 | zhǐ lìng jì cún qì |
| register/ˈredʒɪstə/ | 寄存器 | jì cún qì |
| arithmetic logic unit/əˈrɪθmətɪk ˈlɒdʒɪk ˈjuːnɪt/ | 算术逻辑单元 | suàn shù luó jí dān yuán |
| memory hierarchy | 存储层次 | cún chǔ céng cì |
| cache/kæʃ/ | 高速缓存 | gāo sù huǎn cún |
| locality | 局部性 | jú bù xìng |
| cache line | 缓存行 | huǎn cún xíng |
Same work, ten times slower
- Two loops add up every number in a large table. They do the same additions, yet one runs many times slower than the other.
- The clock speed is the same, and so is the instruction count. The difference is how each loop uses memory, and this lesson explains why.
The fetch-decode-execute cycle
- The processor repeats one loop, the fetch-decode-execute cycle 取指-译码-执行周期. Fetch: the program counter 程序计数器 (PC) gives an address, and the instruction there goes into the instruction register 指令寄存器 (IR).
- Decode turns the instruction into control signals; execute uses the ALU, memory or the PC. With 4-byte instructions the PC then moves on by 4, and a branch writes a new address into it.
Put one pass of the processor's cycle in order.
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Fetch, decode, execute, then the PC moves on (or a branch sets it).
In fetch-decode-execute, the instruction register (IR) is loaded during —
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Fetch reads memory at the PC into the IR; decode then interprets it.
The PC holds 1000 and every instruction is 4 bytes. After three instructions with no branch, what does the PC hold?
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1000 + 3 × 4 = 1012.
Registers and the ALU
- Registers 寄存器 are a few dozen very fast storage places inside the processor. They hold the values the program is working on right now.
- The arithmetic logic unit 算术逻辑单元 (ALU) adds, compares and does logic on register values. Results go back into a register.
The memory hierarchy
- The memory hierarchy 存储层次: registers, then L1, L2 and L3 cache 高速缓存, then DRAM main memory (about 100 ns), then SSD. Each layer is bigger and slower than the one above.
- The reason is cost: fast memory is expensive per byte, and big memory is slow. No single technology is both large and fast.
The memory hierarchy exists because —
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It is a physical trade-off, solved by stacking layers and using locality.
Match each layer to its rough size and speed.
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Each step down is bigger and slower.
Locality makes it work
- Programs show locality 局部性. Temporal locality: data used now is likely to be used again soon. Spatial locality: nearby addresses are likely to be used next.
- So a small fast cache can hold most of what the program touches, and most accesses never reach DRAM.
Reading array elements one after another in address order uses spatial locality.
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Neighbouring addresses come in the same cache line, so the next reads are hits.
Cache lines and data layout
- A cache miss does not fetch one value. It fetches a whole cache line 缓存行, usually 64 adjacent bytes.
- Walking a table row by row uses every byte of each line. Walking it column by column in a large table uses one value per line and misses again and again, which explains the slow loop.
A row-by-row loop beats a column-by-column loop at the same operation count because —
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Consecutive bytes share one line, so layout can beat arithmetic.
Worked example: three instructions
- Memory at address R2 holds 7.
LOAD R1, 0(R2)makes R1 = 7;ADD R3, R1, R1makes R3 = 14;STORE R3, 0(R2)writes 14 back. - Each instruction moves the PC on by 4, so after the three the PC is 12 bytes further on.
Worked example: average access time
- 95% of accesses hit the cache at 1 ns; the other 5% go to DRAM at 100 ns.
- Average $= 0.95 \times 1 + 0.05 \times 100 = 5.95$ ns. The rare misses cost more than all the hits together.
90% of accesses hit the cache at 1 ns and 10% go to DRAM at 100 ns. What is the average access time in ns?
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0.9 × 1 + 0.1 × 100 = 0.9 + 10 = 10.9 ns.
Three common slips
- Mixing up the PC and the IR. The PC holds an address; the IR holds the instruction itself.
- Treating memory time as fixed. A cache hit and a DRAM miss differ about a hundred times.
- Thinking the CPU sees physical addresses. Virtual memory sits in between (lesson 3.5).
Recap
- Fetch (PC to IR), decode (control signals), execute (ALU, memory or PC); then PC + 4 or a branch.
- Registers, cache, DRAM, SSD: each layer bigger, slower and cheaper per byte.
- Locality and 64-byte cache lines make the hierarchy work, so data layout can matter more than the clock.